1. Field of the Invention
This invention is related to integrated circuits. More particularly, this invention relates to multiple function integrated circuits such as Dynamic Random Access Memories (DRAM) having function selection through wiring connections on a second level substrate onto which an integrated circuit is mounted.
2. Background of the Related Art
The structure of a DRAM is well known in the art. Usually a DRAM chip is configured to be organized as a ×1 (by 1), ×4 (by 4), ×8 (by 8), or ×16 (by 16) package by selective destruction of fuses internal to the DRAM chip and by selectively connecting the data input/output pads to pins on a package. The unused pins are not connected to the input/output pads of the undesired or unused data transfer pads. Refer now to FIG. 1 for a schematic drawing of the structure of a DRAM integrated circuit showing the input/output selection function. A DRAM array 100 has multiple banks of arrays of DRAM cells. Address signals are applied to the address I/O's 105 and decoded within column address and row address decoders to select DRAM cells within the DRAM array 100.
Control and timing signals 120 are applied to the control logic and timing generator 115 to provide the necessary control and timing functions for the DRAM array 100.
Upon applying an address to the DRAM array 100, digital data is transferred to or from the DRAM array 100 by the internal data bus 110. The internal data bus 110 is connected between the sense amplifier and I/O bus on each memory bank. The internal data bus 110 may conceptually have a connection for each column of one memory bank, but usually is the maximum data bit width configuration of the DRAM integrated circuit.
The internal data bus 110 is connected to the input/output selector 125. The input/output selector 115 determines the interconnections between the input/output buffers 130 and the internal data bus 110. The selection pins 140 of the input/output selector 125 are connected to the selection networks formed of the resistors 145a, 145b, and 145c and the fuses 150a, 150b, and 150c. A logical one state is applied to the selection pins 140, if a fuse 150a, 150b, and 150c is opened. A logical zero state is applied to the selection pins 140, if a fuse 150a, 150b, and 150c remains intact. The logical states applied to the selection pins 140 determine which connections on the internal data bus 110 are connected to which of the input/output buffers 130. While, as shown, the selector circuits will draw unacceptable amounts of standby current, it is presented here for illustration. Other techniques known in the art are used to form the selection networks.
The input/output buffers 130 are connected to the pads 135. The fuses 150a, 150b, and 150c of the selection network are opened either as a masking during a final metalization or personalization by blowing the fuses 150a, 150b, and 150c with highly intense laser light prior to separation of a wafer containing the DRAM integrated assembly into DRAM modules.
Those input/output pads 135 not used for a configuration are not connected to the module connections during the next level assembly. The fused configuration selection forces the maintenance of inventory of the DRAM die for each desired configuration increasing the difficulty in planning of production of DRAM wafers.
While the structure of the prior art as shown in FIG. 1 is described for a DRAM, other integrated circuit functions such as computational processors (microprocessors, microcontrollers, digital signal processors, etc.), programmable memory, and programmable logic arrays employ metal masking or fuse destruction at the wafer level, and making or omitting connections during attachment of the functional integrated circuit die to a next level package assembly. This complicates the semiconductor processing in that extra masking steps are required for mask programming of desired functions of the functional integrated circuit die. Each function desired requires a unique mask for the selection process, further complicating the semiconductor process. Additionally, fuse destruction adds an extra step in the processing of the functional integrated circuit die.
FIG. 2 shows a process for forming integrated circuit modules. The process begins with the formation 200 of the integrated circuit chip on a semiconductor wafer. The semiconductor process 210 forms the collection of transistors that are the electronic circuits on the semiconductor wafer. The electronic circuits are interconnected by metalization and are also connected to input/output pads by the metalization placed on the surface of the semiconductor wafer. During the metalization, optional functions may be personalized to select optional functions. In the case of the DRAM of FIG. 1, the fuses 150a, 150b, and 150c are either opened or held intact during this process to select the desired input/output organization options. An alternative to selecting the desired input/output organization options of the DRAM of FIG. 1 is exposing the metalization on the surface of the semiconductor substrate that forms the fuses 150a, 150b, and 150c to intense laser light to destroy the appropriate fuses 150a, 150b, and 150c. 
The steps of formation of the integrated circuit chip is common for all the desired selectable functions until the metalization to select the desired functions. The integrated circuit chips then becomes a custom design. Equally, the integrated circuit chip has a common design until the destruction of fuses to create the custom personalization that selects each desired function of the integrated circuit chip.
The semiconductor wafer is placed on a test system and each integrated circuit chip is tested 215 for functionality. The functioning chips are denoted as functional die. The semiconductor wafer is then diced 220 and the functional die are separated for further assembly 225 in a first level or module package. The selection or omission of connections between the functional integrated circuit die and the first level package is a custom design particular to each combination of desired functions.
The input/output pads of the desired functions of the functional die are connected by a method such as wire bonding or tape automated bonding to the pins of the first level package. The input/output pads of the undesired function are omitted during the wire bonding or tape automated bonding. The package is tested 230 and inventoried 235 for further assembly.
The assembly 205 of the second level package begins by forming 240 the substrate of the second level assembly. Multiple layers substrate are formed having interconnection metalization that connects the packaged and tested die to external circuitry that is present either on the second level package or elsewhere within the electronic system. The multiple layers are assembled to form the substrate of the second level assembly.
A solder mask is placed 245 on the second level assembly and a solder paste is placed 250 at all connection points of the packaged and tested die. The packaged and tested die is attached 255 to the second level assembly. In a surface mounted packaging system, the solder paste is melted and the pins of the packaged and tested die fused to the metalization of the second level assembly. The remaining processing of the second level assembly is completed 260.
For integrated circuit modules having multiple functions, the metalization of the second level assembly must be customized. Again, this increases the number of assembly types required to be inventoried.
U.S. Pat. No. 5,360,992 (Lowery et al.) discloses a semiconductor package, which allows pinouts and bond options to be customized after encasement of a semiconductor die. The semiconductor package has two assemblies in a first embodiment and an optional third assembly in a second embodiment.
A first assembly comprises a semiconductor die encased in plastic, ceramic, or other suitable material. All available bond options (bond pads) are routed to the exterior portion of the package by a first assembly frame. Portions of the first assembly frame are exterior to the encasement and terminate in exterior pad portions that can be conductively bonded to.
A second assembly of the invention comprises a second assembly frame that provides a means of input/output (I/O) between the packaged die and a next level of assembly onto which it is installed. The second assembly frame comprises conductive paths to which the exterior pad portions are connected, the first assembly being conductively mounted to the second assembly thereby. With the two-piece embodiment of the invention, the frame of the second assembly determines the pinouts (the pin numbers associated with each of the signals of the device) of the various signals of the die contained within the first assembly.
The optional third assembly, which, if used, is interposed between the first and second assemblies, comprises means for “keying” the exterior pad portion desired locations or the second assembly frame. The assembly can comprise at least two different forms.
In the first form, the third assembly is a nonconductive membrane having voids there through, conductive paths of the second assembly are located in an “X” direction, while the exterior pad portions of first assembly of this form are bars extending in a “Y” direction. By selectively placing the voids in the membrane, the pads of the first assembly can either be connected with the conductive paths of the second assembly or isolated from the conductive paths if no void is formed. Using the X-Y arrangement, any of the bond options can be connected with any of the pinouts. Connecting is accomplished by coating the bars with a conductive material and interposing the insulative membrane between the first and second assemblies. The conductive material fills the voids, thereby passing signals between the first and second assemblies.
In the second form, the third assembly comprises a flex circuit as used with tape automated bonding. The second assembly has a single design, and the layout of the flex circuit determines the pinouts and options of the semiconductor device. The flex circuit is conductively mounted to the first and second assemblies in a fashion consistent with tape automated bonding (TAB) technology, for instance with solder, or by some other means such as conductive epoxy.
U.S. Pat. No. 5,737,767 (Agrawal et al.) teaches a random access memory (RAM) array with a reconfigurable bit width or word width. In one embodiment, a reconfigurable x-y RAM array is provided which includes a memory array comprised of a plurality of RAM cell columns. The RAM cell columns are organized into a number of groups where the number of groups corresponds to the bit width of the memory. Each group contains an equal number of columns so that the number of columns in a group multi number of groups equals the total number of array. The number of columns in a group is reconfigurable according to the present invention. Thus, when the number of columns in a group is smaller, the number of groups is larger and when the number of columns in a larger, the number of groups is smaller. Thus, the bit width of the memory is reconfigurable by modifying the number of columns in a group, since the bit memory corresponds to the number of groups.
To access a word stored in the array, The RAM decodes an address and selects one bit from each column group. Thus, the word size stored by the RAM is determined by the number of columns groups configured in the array.
Agrawal et al. provides multiplexer (mux) logic coupled to each column. Column select logic decodes a memory address and provides select signals corresponding to the address to the mux logic. The mux selects a particular column in the group to be accessed and outputs a column bit signal indicative of the memory state of the selected column.
Column configuration logic is coupled to the mux logic and combines the mux outputs into memory bit signals. The mux outputs combined by the column configuration logic determine the size of the column groups from which a memory bit signal is selected. The column configuration logic may be placed in different modes to configure different column group sizes and thus to reconfigure the bit width of the memory. The column select logic is responsive to the configuration mode and decodes the address for the appropriate column group size.